The conventional approach to electronic packaging and interconnection has been to package individual integrated circuit (IC) chips in a single package and to attach these packages to a printed circuit board to provide interconnection between the individual IC chips. In recent years, this approach has met with problems of speed, size, and interconnection density due to ever constant demands for reduced size and increased performance from such integrated circuit packages.
One solution to many of the above problems is the multichip module (MCM). In an MCM, bare (unpackaged) IC chips are interconnected by means of a miniature printed circuit board whose interconnection pitch may match the pitch of the IC chip. There are presently two main classes of MCM. These are the “chips last MCM” and the “chips first MCM”. In the chips last MCM, the miniature circuit board is fabricated first and then the bare IC chips are attached and interconnected to the circuit board. The method of interconnection is usually wire bond or solder bump. In the chips first MCM, the chips are placed and bonded to a substrate, and a miniature circuit board is then built above the chips. The method of interconnection, usually entails forming IC chips as an integral part of the processing of the circuit board. Currently, the industry uses build-up technology to interconnect IC chips in the chips first MCM. Build-up technology to interconnect IC chips in the chips first MCM is generally known. One such technique that is relevant to the present subject matter is discussed in U.S. Pat. No. 6,159,767.
As mentioned above, the chips first MCM requires placing the IC chips first relative to each other on a substrate. It is generally difficult to maintain consistency during placement and bonding of the IC chips onto a substrate. The inconsistencies in placing and bonding IC chips onto a substrate generally result in coplanarity and alignment problems between the IC chips and the substrate.
Generally, a thicker dielectric layer is required in forming the miniature circuit board over the IC chips to overcome the above-described inconsistency problems. The thicker the dielectric layer, the higher the thermal buildup and the mechanical stress generated during post-processing operations of the multichip module. In addition, the thickness of the dielectric layer formed over the IC chips can vary substantially due to coplanarity problems between the upper surfaces of the IC chips and the dielectric layer. In addition, the cost of raw material used in forming the dielectric layer increases due to its increased thickness. Further, variations in the thickness of the dielectric layer can cause changes in the dielectric properties, such as capacitance. Furthermore, variations in the thickness of the dielectric layer can cause post-processing problems, such as metal deposition rate, varying etch rate, metal coverage, and so on, which can ultimately result in a lower yield.
Thus, there is a need in the art for a technique to form MCMs using build-up technology that can overcome the above-described problems.